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cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 14824 rev. *h revised october 17, 2016 the following document contains information on cypress products. although the document is marked with the name broadcom, the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the cypress ordering part number listed in the table. broadcom ordering part number cypress ordering part number bcm20730a2kml2gt bcm20730a1kml2g bcm20730a1kmlg bcm20730a1kfbgt bcm20730a2kfbg bcm20730a1kfbg bcm20730a1kml2gt bcm20730a2kml2g bcm20730a1kmlgt bcm20730a2kfbgt cyw20730a2kml2gt cyw20730a1kml2g cyw20730a1kmlg CYW20730A1KFBGt cyw20730a2kfbg CYW20730A1KFBG cyw20730a1kml2gt cyw20730a2kml2g cyw20730a1kmlgt cyw20730a2kfbgt for more information please visit our website at www.cypress.com or contact your local sales office for additional information about cypress products and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create new industries with products and so lutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated products and get them to market first . cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record time. to learn more, go to www.cypress.com .
data sheet bcm20730 20730-ds108-r 5300 california avenue ? irvine, ca 92617 ? phone: 949-926-5000 ? fax: 949-926-5203 september 9, 2013 single-chip bluetooth transceiver for wireless input devices general description features the broadcom? bcm20730 is a bluetooth 3.0- compliant, stand-alone baseband processor with an integrated 2.4 ghz transceiver. it is ideal for wireless input device applications including game controllers, keyboards, 3d glasses, remote controls, gestural input devices, and sensor devices. built-in firmware adheres to the bluetooth human interface device (hid) profile and bluetooth device id profile specifications. the bcm20730 radio has been designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. it is fully compliant with bluetooth radio specification 3.0. the single-chip bluetooth transceiver is a monolithic component implemented in a standard digital cmos process and requires minimal external components to make a fully compliant bluetooth device. the bcm20730 is available in three package options: a 32-pin, 5 mm 5 mm qfn, a 40-pin, 6 mm 6 mm qfn, and a 64-pin, 7 mm 7 mm bga. applications ? wireless pointing devices: mice, trackballs, gestural controls ?wireless keyboards ? 3d glasses ?remote controls ? game controllers ? point-of-sale (pos) input devices ?remote sensors ? home automation ? personal health and fitness monitoring ? on-chip support for common keyboard and mouse interfaces eliminates external processor ? programmable keyscan matrix interface, up to 8 20 key-scanning matrix ? 3-axis quadrature signal decoder ? shutter control for 3d glasses ? infrared modulator ? ir learning ? triac control ? triggered broadcom fast connect ? supports adaptive frequency hopping ? excellent receiver sensitivity ? bluetooth specification 3.0 compatible, including enhanced power control (unicast connectionless data) ? bluetooth hid profile version 1.0 compliant ? bluetooth device id profile version 1.3 compliant ? bluetooth avrcp-ct profile version 1.3 compliant ? 10-bit auxiliary adc with 28 analog channels ? on-chip support for serial peripheral interface (master and slave modes) ? broadcom serial communi cations (bsc) interface (compatible with philips? (now nxp) i 2 c slaves) ? programmable output power control meets class 2 or class 3 requirements ? class 1 operation supported with external pa and t/r switch ? integrated arm cortex?-m3 based microprocessor core ? on-chip power-on reset (por) ? support for eeprom and serial flash interfaces ? integrated low-dropout regulator (ldo) ? on-chip software controlled power management unit ? three package types are available: ? 32-pin qfn package (5 mm 5 mm) ? 40-pin qfn package (6 mm 6 mm) ? 64-pin bga package (7 mm 7 mm) ? rohs compliant
revision history bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 2 ? broadcom confidential figure 1: functional block diagram keyboard matrix scanner w/fifo 3-axis mouse signal controller processing unit (arm -cm3) system bus bluetooth baseband core 2.4 ghz radio rf control and data t/r switch rf i/o gpio control/ status registers frequency synthesizer 14 gpio on the 32-pin qfn 24 mhz ref. xtal pmu i/o ring bus i/o ring control registers peripheral interface block 1.2v vdd_core domain vdd_io domain wake 1.2v ldo 1.425v to 3.6v 1.2v vdd_core 320k rom 60k ram bsc/spi master interface (bsc is i 2 c- compa ? ble) sda/ mosi scl/ sck 6 quadrature inputs (3 pair) + high current driver controls 8 x 20 scan matrix 40 gpio 32 khz lpclk 28 adc inputs 24 mhz hclk (24 mhz to 1 mhz) autocal miso 1.2v vdd_rf domain pwm wdt 128 khz lpo 4 32 khz lpclk 128 khz lpclk 32 khz y?o~}??}vo power 1.62v to 3.6v vdd_io 1.2v por 1.2v test uart ir i/o ir mod. and learning spi m/s mia por 28 adc inputs ct gp adc vss, vddo, vddc periph uart uart_rxd uart_txd tx rx rts_n cts_n muxed on gpio volt. trans 3-d glasses and triac 1.62v to 3.6v
revision history bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 3 ? broadcom confidential revision history revision date change description 20730-ds108-r 09/09/13 revised: ? section : ?shutter control for 3d glasses,? on page 13 ? table 27: ?ordering information,? on page 58 added: ? table 15: ?esd tolerance,? on page 45 20730-ds107-r 10/10/12 revised: ? ?spi timing? on page 49 20730-ds106-r 09/20/11 changed from a preliminary data sheet to a data sheet. 20730-ds105-r 06/29/11 added: ? figure 9: ?32-pin qfn ball map,? on page 39 ? figure 16: ?32-pin qfn package,? on page 52 ? table 20: ?bcm20730 5 5 1 mm qfn, 32-pin tape reel specifications,? on page 55 revised: ? general description and features on cover ? figure 1: ?functional block diagram,? on page 2 ??adc port? on page 17 ? table 2: ?bcm20730 first spi set (master mode),? on page 18 ? table 2: ?bcm20730 first spi set (master mode),? on page 18 ? table 2: ?bcm20730 first spi set (master mode),? on page 18 ? figure 5: ?external reset timing,? on page 22 ??gpio port? on page 27 ? ?bbc power management? on page 29 ? table 7: ?pin descriptions,? on page 30 ? table 8: ?gpio pin descriptions,? on page 32 ? table 12: ?adc specifications,? on page 44 20730-ds104-r 05/09/2011 revised: ? figure 1: ?functional block diagram,? on page 2 ??adc port? on page 17 ? table 10: ?power supply,? on page 39 20730-ds103-r 04/06/11 revised: ? table 14: ?current consumption,? on page 42 ? table 23: ?ordering information,? on page 54
revision history bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 4 ? broadcom confidential 20730-ds102-r 03/23/11 added: ? table 1: ?adc modes,? on page 18 revised: ? figure 1: ?functional block diagram,? on page 2 ??adc port? on page 17 ? ?internal ldo regulator? on page 22 ??uart interface? on page 23 ? table 6: ?xtal oscillator characteristics,? on page 25 ? table 8: ?gpio pin descriptions,? on page 30 ? table 10: ?power supply,? on page 39 ? table 11: ?ldo regulator electrical specifications,? on page 40 ? table 12: ?adc specifications,? on page 41 ? table 14: ?current consumption,? on page 42 ? table 15: ?receiver rf specifications,? on page 43 ? table 16: ?transmitter rf specifications,? on page 44 ? table 18: ?spi interface timing specifications,? on page 46 ? table 21: ?bcm20730 6 6 1 mm qfn, 40-pin tape reel specifications,? on page 52 ? table 22: ?bcm20730 7 7 .8 mm wfbga, 64-pin tape reel specifications,? on page 52 deleted: ? placeholder for figure 4: triac control ? placeholder for figure 18: bcm20730, 6 x 6 qfn package tray ? placeholder for figure 19: bcm20730, 7 x 7 fbga package tray revision date change description
broadcom?, the pulse logo, connecting everything?, and the connecting everything logo are among the registered trademarks of broadcom corporation and/or its subsidiaries in the united states, certain other countries, and/or the eu. bluetooth? is a trademark of the bluetooth si g. any other trademarks or trade names mentioned are the property of their respective owners. confidential and proprietary information: this document and the software are proprietary properties of broadcom corporation. this software package may only be used in accordance with the broadcom corporation license agreement. this data sheet (including, without limitation, the broa dcom component(s) identified herein) is not designed, intended, or certified for use in an y military, nuclear, medical, mass tr ansportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as-is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitness for a partic ular purpose, and non-infringement. broadcom corporation 5300 california avenue irvine, ca 92617 ? 2013 by broadcom corporation all rights reserved printed in the u.s.a. 20730-ds101-r 6/25/10 added: ? ?shutter control for 3d glasses? on page 10. ? ?infrared modulator? on page 10. ? ?infrared learning? on page 11. ? ?triac control? on page 12. ? ?broadcom proprietary control signalling and triggered baseband fast connect? on page 12. ? figure 5: ?internal reset timing,? on page 17. ? figure 6: ?external reset timing,? on page 17. ? figure 10: ?40-pin qfn ball map,? on page 33. ? figure 11: ?64-pin bga ball map,? on page 34. ? ?spi timing? on page 41. ? figure 16: ?40-pin qfn,? on page 44. ? figure 17: ?64-pin fbga,? on page 45. revised: ? ?microprocessor unit? on page 16. ? table 6: ?pin descriptions,? on page 25. ? table 11: ?adc specifications,? on page 36. ? table 14: ?receiver rf specifications,? on page 38. ? table 15: ?transmitter rf specifications,? on page 39. ? table 21: ?ordering information,? on page 50. 20730-ds100-ri 4/27/10 initial release. revision date change description
table of contents bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 6 ? broadcom confidential table of contents about this document ............................................................................................................................... ....11 purpose and audience ........................................................................................................... ................11 acronyms and abbreviations..................................................................................................... ............11 references ..................................................................................................................... ........................11 technical support ............................................................................................................................... ..........11 section 1: functional description .................................................................................... 12 keyboard scanner ............................................................................................................................... ..........12 theory of operation ............................................................................................................ ..................12 idle ........................................................................................................................... .......................12 scan ........................................................................................................................... .....................12 scan end ....................................................................................................................... ..................13 mouse quadrature signal decoder ..............................................................................................................13 theory of operation ............................................................................................................ ..................13 shutter control for 3d glasses .....................................................................................................................13 infrared modulator ............................................................................................................................... .......14 infrared learning ............................................................................................................................... ...........15 triac control ............................................................................................................................... ..................15 broadcom proprietary control signaling and triggered broadcom fast connect .....................................15 bluetooth baseband core ............................................................................................................................16 frequency hopping generator .................................................................................................... ..........16 e0 encryption .................................................................................................................. .......................16 link control layer ............................................................................................................. .....................16 adaptive frequency hopping..................................................................................................... ............17 bluetooth version 3.0 features ................................................................................................. ............17 test mode support .............................................................................................................. ..................17 adc port ............................................................................................................................... ........................17 serial peripheral interface ...........................................................................................................................18 microprocessor unit ............................................................................................................................... ......21 eeprom interface............................................................................................................... ...................21 serial flash interface......................................................................................................... .....................21 internal reset................................................................................................................. ........................22 external reset ................................................................................................................. .......................22 integrated radio transceiver .......................................................................................................................23 transmitter path ............................................................................................................... .....................23
table of contents bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 7 ? broadcom confidential digital modulator.............................................................................................................. ..............23 power amplifier ................................................................................................................ ..............23 receiver path .................................................................................................................. .......................23 digital demodulator and bit synchronizer .....................................................................................23 receiver signal strength indicator............................................................................................. .....23 local oscillator............................................................................................................... ........................24 calibration.................................................................................................................... ..........................24 internal ldo regulator ......................................................................................................... .................24 peripheral transport unit ............................................................................................................................24 broadcom serial communications interface ....................................................................................... ..24 uart interface................................................................................................................. ......................25 clock frequencies ............................................................................................................................... ..........25 crystal oscillator ............................................................................................................. .......................25 hid peripheral block ........................................................................................................... ............26 32 khz crystal oscilla tor ...................................................................................................... ...........26 gpio port ............................................................................................................................... .......................27 port 0?port 1, port 8?port 23, and port 28?port 38............................................................................. .27 port 26?port 29................................................................................................................ ......................27 pwm ............................................................................................................................... ..............................27 power management unit .............................................................................................................................28 rf power management ............................................................................................................ .............28 host controller power management............................................................................................... ......29 bbc power management ........................................................................................................... ............29 section 2: pin assignments.............................................................................................. 30 pin descriptions ............................................................................................................................... .............30 ball maps ............................................................................................................................... .......................39 section 3: specifications.................................................................................................. 42 electrical characteristics ..............................................................................................................................4 2 rf specifications ............................................................................................................................... ............46 timing and ac characteristics ......................................................................................................................48 uart timing .................................................................................................................... ......................48 spi timing..................................................................................................................... ..........................49 bsc interface timing........................................................................................................... ...................51 section 4: mechanical information.................................................................................. 53 tape reel and packaging specifications ......................................................................................... .......56
table of contents bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 8 ? broadcom confidential section 5: ordering information ...................................................................................... 58 appendix a: acronyms and abbreviations....................................................................... 59
list of figures bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 9 ? broadcom confidential list of figures figure 1: functional block diagram............................................................................................. .......................2 figure 2: infrared tx.......................................................................................................... ...............................14 figure 3: infrared rx.......................................................................................................... ...............................15 figure 4: internal reset timing ................................................................................................ ........................22 figure 5: external reset timing................................................................................................ ........................22 figure 6: recommended oscillator config uration ? 12 pf load crystal..........................................................25 figure 7: 32 khz oscillator block diagram...................................................................................... ..................26 figure 8: pwm channel block diagram............................................................................................ ................28 figure 9: 32-pin qfn ball map .................................................................................................. .......................39 figure 10: 40-pin qfn ball map ................................................................................................. ......................40 figure 11: 64-pin bga ball map ................................................................................................. ......................41 figure 12: uart timing ......................................................................................................... ...........................48 figure 13: spi timing diagram.................................................................................................. ........................49 figure 14: bsc interface timing diagram ........................................................................................ .................52 figure 15: 32-pin qfn package .................................................................................................. ......................53 figure 16: 40-pin qfn package .................................................................................................. ......................54 figure 17: 64-pin fbga package................................................................................................. ......................55 figure 18: pin 1 orientation ................................................................................................... ..........................57
list of tables bcm20730 data sheet broadcom september 9, 2013 ? 20730-ds108-r page 10 ? broadcom confidential list of tables table 1: adc modes ............................................................................................................. ............................18 table 2: bcm20730 first spi set (master mode) .................................................................................. ...........18 table 3: bcm20730 second spi set (master mode)................................................................................. ........18 table 4: bcm20730 second spi set (slave mode).................................................................................. ..........19 table 5: reference crystal electrical specifications ........................................................................... ..............26 table 6: xtal oscillator ch aracteristics ....................................................................................... ....................27 table 7: pin descriptions ...................................................................................................... ............................30 table 8: gpio pin descriptions ................................................................................................. ........................32 table 9: maximum electrical rating ............................................................................................. ....................42 table 10: power supply ......................................................................................................... ...........................42 table 11: ldo regulator electrical specifications .............................................................................. ..............43 table 12: adc specifications ................................................................................................... .........................44 table 13: digital level ........................................................................................................ ..............................44 table 14: current consumption ................................................................................................. .....................45 table 15: esd tolerance ........................................................................................................ ...........................45 table 16: receiver rf specifications ........................................................................................... .....................46 table 17: transmitter rf specifications ........................................................................................ ...................47 table 18: uart timing specifications ........................................................................................... ...................48 table 19: spi1 timing values ? sclk = 12 mhz and vddm = 3.2v ..................................................................4 9 table 20: spi1 timing values ? sclk = 6 mhz and vddm = 1.62v ..................................................................5 0 table 21: spi2 timing values ? sclk = 12 mhz and vddm = 3.2v ..................................................................5 0 table 22: spi2 timing values ? sclk = 6 mhz and vddm = 1.62v ..................................................................5 1 table 23: bsc interface timing specifications.................................................................................. ................51 table 24: bcm20730 5 5 1 mm qfn, 32-pin tape reel specifications.......................................................56 table 25: bcm20730 6 6 1 mm qfn, 40-pin tape reel specifications.......................................................56 table 26: bcm20730 7 7 0.8 mm wfbga, 64-pin tape reel specifications ..............................................56 table 27: ordering information ................................................................................................. ......................58
about this document broadcom september 9, 2013 ? 20730-ds108-r page 11 ? bcm20730 data sheet broadcom confidential about this document purpose and audience this data sheet provides a description of the major blocks, interfaces, pin assignments, and specifications of the bcm20730 single-chip bluetooth transceiver. this is a required document for designers responsible for adding the bcm20730 bluetooth transceiver to wireless input device applications including game controllers, keyboards, 3d glasses, remote controls, gestural input devices, and sensor devices. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. acronyms and abbreviations in this document are also defined in appendix a: ?acronyms and abbreviations,? on page 59 . for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . references the references in this section may be used in conjunction with this document. for broadcom documents, replace the ?x? in the document number with the largest number available in the repository to ensure that you have the most current version of the document. technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads & support site ( http://www.broadcom.com/support/ ). note: broadcom provides customer access to technical documentation and software through its customer support portal (csp) and downloads & support site (see technical support ). document name number broadcom items [1] single-chip bluetooth? transceiver and baseband processor 20702-ds10x-r
functional description broadcom september 9, 2013 ? 20730-ds108-r page 12 ? bcm20730 data sheet broadcom confidential section 1: functional description keyboard scanner the keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host microcontroller to intervene. the scanner has the following features: ? ability to turn off its clock if no keys pressed. ? sequential scanning of up to 160 keys in an 8 x 20 matrix. ? programmable number of columns from 1 to 20. ? programmable number of rows from 1 to 8. ? 16-byte key-code buffer (can be augmented by firmware). ? 128 khz clock ? allows scanning of full 160-key matrix in about 1.2 ms. ? n-key rollover with selective 2-key lockout if ghost is detected. ? keys are buffered until host microcontroller has a chance to read it, or until overflow occurs. ? hardware debouncing and noise/glitch filtering. ? low-power consumption. single-digit a-level sleep current. theory of operation the key scan block is controlled by a state machine with the following states: idle the state machine begins in the idle state. in this state, all column outputs are driven high. if any key is pressed, a transition occurs on one of the row inputs. this transition causes the 128 khz clock to be enabled (if it is not already enabled by another peripheral) and the state machine to enter the scan state. also in this state, an 8- bit row-hit register and an 8-bit key-index counter is reset to 0. scan in the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. once the last row is reached, the row counter is reset and the column counter is incremented. this cycle repeats until the row and column counters are both at their respective terminal count values. at that point, the state machine moves into the scan-end state. as the keys are being scanned, the key-index counter is incremented. this counter is the value compared to the modifier key codes stored, or in the key-code buffer if the key is not a modifier key. it can be used by the microprocessor as an index into a lookup table of usage codes.
mouse quadrature signal decoder broadcom september 9, 2013 ? 20730-ds108-r page 13 ? bcm20730 data sheet broadcom confidential also, as the n-th row is scanned, the row-hit register is ored with the current 8-bit row input values if the current column contains two or more row hits. during the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit was de tected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set to indicate this. scan end this state determines whether any keys were detected while in the scan state. if yes, the state machine returns to the scan state. if no, the state machine returns to the idle state, and the 128 khz clock request signal is made inactive. the microcontroller can poll the key status register. mouse quadrature signal decoder the mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by optomechanical mouse apparatus. the decoder has the following features: ? three pairs of inputs for x, y, and z (typical scroll wheel) axis signals. each axis has two options: ? for the x axis, choose p2 or p32 as x0 and p3 or p33 as x1. ? for the y axis, choose p4 or p34 as y0 and p5 or p35 as y1. ? for the z axis, choose p6 or p36 as z0 and p7 or p37 as z1. ? control of up to four external high current gpios to power external optoelectronics: ? turn-on and turn-off time can be staggered for each hc-gpio to avoid simultaneous switching of high currents and having multiple high-current devices on at the same time. ? sample time can be staggered for each axis. ? sense of the control signal can be active high or active low. ? control signal can be tristated for off condition or driven high or low, as appropriate. theory of operation the mouse decoder block has four 16-bit pwms for controlling external quadrature devices and sampling the quadrature inputs at its core. the gpio signals may be used to control such items as leds, external ics that may emulate quadrature signals, photodiodes, and photodetectors. shutter control for 3d glasses the bcm20730, combined with the bcm20702, provides full system s upport for 3d glasses on televisions. the bcm20702 gets frame synchronization signals from the tv, converts them into proprietary timing control messages, then passes these messages to the bcm20730. the bcm20730 uses these messages to synchronize the shutter control for the 3d glasses with the television frames.
infrared modulator broadcom september 9, 2013 ? 20730-ds108-r page 14 ? bcm20730 data sheet broadcom confidential the bcm20730 can provide up to four synchronized control signals for left and right eye shutter control. these four lines can output pulses with microsecond resolution for on and off timing. the total cycle time can be set for any period up to 65535 msec. the pulses are synchronized to each other for left and right eye shutters. the bcm20730 seamlessly adjusts the timing of the control signals based on control messages from the bcm20702, ensuring that the 3d glasses remain synchronized to the tv display frame. 3d hardware control on the bcm20730 works independently of the rest of the system. the bcm20730 negotiates sniff with the bcm20702 and, except for sniff resynchronization periods, most of the bcm20730 circuitry remains in a low power state while the 3d glasses subsystem continues to provide shutter timing and control pulses. this significantly reduces total system power consumption. the bcm20730a2 has the new bt sig 3dg profile, as well as legacy mode 3dg, included in rom. this allows it to support a smaller and lower cost external memory of 4 kb. infrared modulator the bcm20730 includes hardware support for infrared tx. the hardware can transmit both modulated and unmodulated waveforms. for modulated waveforms, hardware inserts the desired carrier frequency into all ir transmissions. ir tx can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral uart transmitter. if descriptors are used, they include ir on/off state and the duration between 1?32767 sec. the bcm20730 ir tx firmware driver inserts this information in a hardware fifo and makes sure that all descriptors are played out without a glitch due to underrun. see figure 2 . figure 2: infrared tx
infrared learning broadcom september 9, 2013 ? 20730-ds108-r page 15 ? bcm20730 data sheet broadcom confidential infrared learning the bcm20730 includes hardware support for infrared learning. the hardware can detect both modulated and unmodulated signals. for modulated signals, the bcm20730 can detect carrier frequencies between 10 khz and 500 khz and the duration that the signal is present or absent. the bcm20730 firmware driver supports further analysis and compression of learned signal. the learned signal can then be played back through the bcm20730 ir tx subsystem. see figure 3 . figure 3: infrared rx triac control the bcm20730 includes hardware support for zero-crossing detection and trigger control for up to four triacs. the bcm20730 detects zero-crossing on the ac zero detection line and uses that to provide a pulse that is offset from the zero-crossing. this allows the bcm20730 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an input event. broadcom proprietary control signaling and triggered broadcom fast connect broadcom proprietary control signaling (bpcs) and triggered broadcom fast connect (tbfc) are broadcom- proprietary baseband (acl) suspension and low latency reconnection mechanisms that reestablish the baseband connection with the peer controller that also supports bpcs/tbfc. the bcm20730 uses bpcs primitives to allow a human interface device (hid) to suspend all rf traffic after a configurable idle period with no reportable activity. to conserve power, it can then enter one of its low power states while still logically remaining connected at the l2cap and hid layers with the peer device. when an event requires the hid to deliver a report to the peer device, the bcm20730 uses the tbfc and bpcs mechanisms to reestablish the baseband connection and can immediately resume l2cap traffic, greatly reducing latency between the event and delivery of the report to the peer device.
bluetooth baseband core broadcom september 9, 2013 ? 20730-ds108-r page 16 ? bcm20730 data sheet broadcom confidential certain applications may make use of the bcm20730 baseband fast connect (bfc) mechanism for power savings and lower latencies not achievable by using even long sniff intervals by completely eliminating the need to maintain an rf link, while still being able to establish acl and l2cap connections much faster than regular methods. bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time-critical functions required for high performance bluetooth operation. the bbc manages the buffering, se gmentation, and data routing for all connections. it also buffers data that passes through it, handles data flow control, schedules acl tx/rx transactions, monitors bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes hci packets. in addition to these functions, it independently handles hci event types and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase tx/rx data reliability and security before sending over the air: ? receive functions: symbol timing recovery, data deframing, forward error correction (fec), header error control (hec), cyclic redundancy check (crc), data decryption, and data dewhitening. ? transmit functions: data framing, fec generation, hec generation, crc generation, link key generation, data encryption, and data whitening. frequency hopping generator the frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state, bluetooth clock, and device address. e0 encryption the encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide minimal processor intervention. link control layer the link control layer is part of the bluetooth link control functions that are implemented in dedicated logic in the link control unit (lcu). this layer consists of the command controller, which takes software commands, and other controllers that are activated or configured by the command controller to perform the link control tasks. each task performs a different bluetooth link controller state. standby and connection are the two major states. in addition, there are five substates: page, page scan, inquiry, inquiry scan, and sniff.
adc port broadcom september 9, 2013 ? 20730-ds108-r page 17 ? bcm20730 data sheet broadcom confidential adaptive frequency hopping the bcm20730 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map selection. the link quality is determined by using both rf and baseband signal processing to provide a more accurate frequency hop map. bluetooth version 3.0 features the bcm20730 supports bluetooth 3.0, including the following options: ?enhanced power control ? unicast connectionless data ? hci read encryption key size command the bcm20730 also supports the following bluetooth version 2.1 features: ? extended inquiry response ? sniff subrating ? encryption pause and resume ? secure simple pairing ? link supervision timeout changed event ? erroneous data reporting ? non-automatically-flushable packet boundary flag ? security mode 4 test mode support the bcm20730 fully supports bluetooth test mode, as described in part 1 of the bluetooth 3.0 specification. this includes the transmitter tests, normal and delayed loopback tests, and the reduced hopping sequence. in addition to the standard bluetooth test mode, the device supports enhanced testing features to simplify rf debugging and qualification as well as type-approval testing. adc port the bcm20730 contains a 16-bit adc (effective number of bits is 10). additionally: ? there are 28 analog input channels in the 64-pin package, 12 analog input channels in the 40-pin package, and 9 analog input channels in the 32-pin package. all channels are multiplexed on various gpios. ? the conversion time is 10 s. ? there is a built-in reference with supply- or band-gap based reference modes. ? the maximum conversion rate is 187 khz. ? there is a rail-to-rail input swing.
serial peripheral interface broadcom september 9, 2013 ? 20730-ds108-r page 18 ? bcm20730 data sheet broadcom confidential the adc consists of an analog adc core that performs the actual analog-to-digital conversion and digital hardware that processes the output of the adc core into valid adc output samples. directed by the firmware, the digital hardware also controls the input multiplexers that select the adc input signal v inp and the adc reference signals v ref . serial peripheral interface the bcm20730 has two independent spi interfaces. one is a master-only interface and the other can be either a master or a slave. each interface has a 16-byte transmit buffer and a 16-byte receive buffer. to support more flexibility for user applications, the bcm20730 has optional i/o ports that can be configured individually and separately for each functional pin, as shown in table 2 . the bcm20730 acts as an spi master device that supports 1.8v or 3.3v spi slaves, as shown in table 2 . the bcm20730 can also act as an spi slave device that supports a 1.8v or 3.3v spi master, as shown in table 2 . table 1: adc modes mode enob (typical) maximum sampling rate (khz) latency a ( s) a. settling time after switching channels. 0 13 5.859 171 1 12.6 11.7 85 212 46.875 21 3 11.5 93.75 11 410 187 5 table 2: bcm20730 first spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a a. any gpio can be used as spi_cs when spi is in master mode. configuration set 1 scl sda p24 ? configuration set 2 scl sda p26 ? configuration set 3 (default for serial flash) scl sda p32 p33 configuration set 4 scl sda p39 ? table 3: bcm20730 second spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a configuration set 1 p3 p0 p1 ? configuration set 2 p3 p0 p5 ? configuration set 3 p3 p2 p1 ? configuration set 4 p3 p2 p5 ?
serial peripheral interface broadcom september 9, 2013 ? 20730-ds108-r page 19 ? bcm20730 data sheet broadcom confidential configuration set 5 p3 p4 p1 ? configuration set 6 p3 p4 p5 ? configuration set 7 p3 p27 p1 ? configuration set 8 p3 p27 p5 ? configuration set 9 p3 p38 p1 ? configuration set 10 p3 p38 p5 ? configuration set 11 p7 p0 p1 ? configuration set 12 p7 p0 p5 ? configuration set 13 p7 p2 p1 ? configuration set 14 p7 p2 p5 ? configuration set 15 p7 p4 p1 ? configuration set 16 p7 p4 p5 ? configuration set 17 p7 p27 p1 ? configuration set 18 p7 p27 p5 ? configuration set 19 p7 p38 p1 ? configuration set 20 p7 p38 p5 ? configuration set 21 p24 p0 p25 ? configuration set 22 p24 p2 p25 ? configuration set 23 p24 p4 p25 ? configuration set 24 p24 p27 p25 ? configuration set 25 p24 p38 p25 ? configuration set 26 p36 p0 p25 ? configuration set 27 p36 p2 p25 ? configuration set 28 p36 p4 p25 ? configuration set 29 p36 p27 p25 ? configuration set 30 p36 p38 p25 ? a. any gpio can be used as spi_cs when spi is in master mode. table 4: bcm20730 second spi set (slave mode) a pin name spi_clk spi_mosi spi_miso spi_cs configuration set 1 p3 p0 p1 p2 configuration set 2 p3 p0 p5 p2 configuration set 3 p3 p4 p1 p2 configuration set 4 p3 p4 p5 p2 configuration set 5 p7 p0 p1 p2 table 3: bcm20730 second spi set (master mode) (cont.) pin name spi_clk spi_mosi spi_miso spi_cs a
serial peripheral interface broadcom september 9, 2013 ? 20730-ds108-r page 20 ? bcm20730 data sheet broadcom confidential configuration set 6 p7 p0 p5 p2 configuration set 7 p7 p4 p1 p2 configuration set 8 p7 p4 p5 p2 configuration set 9 p3 p0 p1 p6 configuration set 10 p3 p0 p5 p6 configuration set 11 p3 p4 p1 p6 configuration set 12 p3 p4 p5 p6 configuration set 13 p7 p0 p1 p6 configuration set 14 p7 p0 p5 p6 configuration set 15 p7 p4 p1 p6 configuration set 16 p7 p4 p5 p6 configuration set 17 p24 p27 p25 p26 configuration set 18 p24 p33 p25 p26 configuration set 19 p24 p38 p25 p26 configuration set 20 p36 p27 p25 p26 configuration set 21 p36 p33 p25 p26 configuration set 22 p36 p38 p25 p26 configuration set 23 p24 p27 p25 p32 configuration set 24 p24 p33 p25 p32 configuration set 25 p24 p38 p25 p32 configuration set 26 p36 p27 p25 p32 configuration set 27 p36 p33 p25 p32 configuration set 28 p36 p38 p25 p32 configuration set 29 p24 p27 p25 p39 configuration set 30 p24 p33 p25 p39 configuration set 31 p24 p38 p25 p39 configuration set 32 p36 p27 p25 p39 configuration set 33 p36 p33 p25 p39 configuration set 34 p36 p38 p25 p39 a. additional configuration sets are available upon request. table 4: bcm20730 second spi set (slave mode) a pin name spi_clk spi_mosi spi_miso spi_cs
microprocessor unit broadcom september 9, 2013 ? 20730-ds108-r page 21 ? bcm20730 data sheet broadcom confidential microprocessor unit the bcm20730 microprocessor unit (pu) executes software from the link control (lc) layer up to the application layer components that ensure adherence to the bluetooth human interface device (hid) profile and audio/video remote control profile (avrcp). the microprocessor is based on an arm cortex?-m3, 32-bit risc processor with embedded ice-rt debug and jtag interface units. the pu has 320 kb of rom for program storage and boot-up, 60 kb of ram for scratch-pad data, and patch ram code. the internal boot rom provides power-on reset flexibility, which enables the same device to be used in different hid applications with an external serial eepro m or with an external serial flash memory. at power- up, the lowest layer of the protocol stack is executed from the internal rom memory. external patches may be applied to the rom-based firmware to provide flexibility for bug fixes and feature additions. the device can also support the integration of user applications. eeprom interface the bcm20730 provides a broadcom serial control (bsc) master interface. the bsc is programmed by the cpu to generate four types of bsc bus transfers: read-only, write-only, combined read/write, and combined write/ read. bsc supports both low-speed and fast mode devices. the bsc is compatible with a philips? (now nxp) i 2 c slave device, except that master arbitration (multiple i 2 c masters contending for the bus) is not supported. the eeprom can contain customer application configuration information including: application code, configuration data, patches, pairing information, bd_addr, baud rate, sdp service record, and file system information used for code. native support for the microchip? 24lc128, microchip 24aa128, and st micro? m24128-br is included. serial flash interface the bcm20730 includes an spi master controller that can be used to access serial flash memory. the spi master contains an ahb slave interface, transmit and receive fifos, and the spi core phy logic. devices natively supported include the following: ? atmel? at25bcm512b ? mxic? mx25v512zui-20g
microprocessor unit broadcom september 9, 2013 ? 20730-ds108-r page 22 ? bcm20730 data sheet broadcom confidential internal reset figure 4: internal reset timing external reset the bcm20730 has an integrated power-on reset circuit that completely resets all circuits to a known power- on state. an external active low reset signal, reset_n, can be used to put the bcm20730 in the reset state. the reset_n pin has an internal pull-up resistor and, in most applications, it does not require that anything be connected to it. reset_n should only be released after the vddo supply voltage level has been stabilized. figure 5: external reset timing vddo vddo por vddc vddo por threshold vddo por delay ~ 2 ms vddc por vddc por threshold vddc por delay ~ 2 ms baseband reset crystal warm-up delay: ~ 5 ms crystal enable start reading eeprom and firmware boot reset_n pulse width >50 s crystal enable baseband reset start reading eeprom and firmware boot crystal warm-up delay: ~ 5 ms
integrated radio transceiver broadcom september 9, 2013 ? 20730-ds108-r page 23 ? bcm20730 data sheet broadcom confidential integrated radio transceiver the bcm20730 has an integrated radio transceiver that is optimized for 2.4 ghz bluetooth? wireless systems. it has been designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. it is fully compliant with bluetooth radio specification 3.0 and meets or exceeds the requirements to provide the highest communication link quality of service. transmitter path the bcm20730 features a fully integrated transmitter. the baseband transmit data is gfsk modulated in the 2.4 ghz ism band. digital modulator the digital modulator performs the data modulation and filtering required for the gfsk signal. the fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. power amplifier the bcm20730 has an integrated power amplifier (pa) that can transmit up to +4 dbm for class 2 operation. receiver path the receiver path uses a low if scheme to downconver t the received signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology, which has built-in out-of-band attenuation, enables the bcm20730 to be used in most applications without off-chip filtering. digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. receiver signal strength indicator the radio portion of the bcm20730 provides a receiver signal strength indicator (rssi) to the baseband. this enables the controller to take part in a bluetooth power- controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.
peripheral transport unit broadcom september 9, 2013 ? 20730-ds108-r page 24 ? bcm20730 data sheet broadcom confidential local oscillator the local oscillator (lo) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the bcm20730 uses an internal loop filter. calibration the bcm20730 radio transceiver features a self-contained automated calibration scheme. no user interaction is required during normal operation or during manufacturing to provide optimal performance. calibration compensates for filter, matching network, and amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. calibration takes process and temperature variations into account, and it takes place transparently during normal operation and hop setting times. internal ldo regulator the bcm20730 has an integrated 1.2v ldo regulator that provides power to the digital and rf circuits. the 1.2v ldo regulator operates from a 1.425v to 3.63v input supply with a 30 ma maximum load current. peripheral transport unit broadcom serial communications interface the bcm20730 provides a 2-pin master bsc interface, which can be used to retrieve configuration information from an external eeprom or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ics used in mouse devices. the bsc interface is compatible with i 2 c slave devices. the bsc does not support multimaster capability or flexible wait-state insertion by either master or slave devices. the following transfer clock rates are supported by the bsc: ?100 khz ?400 khz ? 800 khz (not a standard i 2 c-compatible speed.) ? 1 mhz (compatibility with high-speed i 2 c-compatible devices is not guaranteed.) the following transfer types are supported by the bsc: ? read (up to 16 bytes can be read.) ? write (up to 16 bytes can be written.) ? read-then-write (up to 16 bytes can be read and up to 16 bytes can be written.) ? write-then-read (up to 16 bytes can be written and up to 16 bytes can be read.) hardware controls the transfers, requiring minimal firmware setup and supervision. note: always place the decoupling capacitors near the pins as closely together as possible.
clock frequencies broadcom september 9, 2013 ? 20730-ds108-r page 25 ? bcm20730 data sheet broadcom confidential the clock pin (scl) and data pin (sda) are both open-dra in i/o pins. pull-up resistors external to the bcm20730 are required on both the scl and sda pins for proper operation. uart interface the uart is a standard 2-wire interface (rx and tx) a nd has adjustable baud rates from 9600 bps to 1.5 mbps. the baud rate can be selected via a vendor-specific uart hci command. the interface supports the bluetooth 3.0 uart hci (h5) specification. the default baud rate for h5 is 115.2 kbaud. both high and low baud rates can be supported by running the uart clock at 24 mhz. the bcm20730 uart operates correctly with the host uart as long as the combined baud rate error of the two devices is within 5%. clock frequencies the bcm20730 is set with crystal frequency of 24 mhz. crystal oscillator the crystal oscillator requires a crystal with an accuracy of 20 ppm as defined by the bluetooth specification. two external load capacitors in the range of 5 pf to 30 pf are required to work with the crystal oscillator. the selection of the load capacitors is crystal dependent. table 5 on page 26 shows the recommended crystal specification. figure 6: recommended oscillator configuration ? 12 pf load crystal 22 pf 20 pf crystal xin xout
clock frequencies broadcom september 9, 2013 ? 20730-ds108-r page 26 ? bcm20730 data sheet broadcom confidential hid peripheral block the peripheral blocks of the bcm20730 all run from a single 128 khz low-power rc oscillator. the oscillator can be turned on at the request of any of the peripherals. if the peripheral is not enabled, it shall not assert its clock request line. the keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock request line if a keypress is detected. 32 khz crystal oscillator figure 7 shows the 32 khz crystal (xtal) oscillator with external components and table 6 on page 27 lists the oscillator?s characteristics. it is a standard pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. the hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mv. this circuit can be operated with a 32 khz or 32.768 khz crystal oscillator or be driven with a clock input at similar frequency. the default component values are: r1 = 10 m , c1 = c2 = ~10 pf. the values of c1 and c2 are used to fine-tune the oscillator. figure 7: 32 khz oscillator block diagram table 5: reference crystal electrical specifications parameter conditions minimum typical maximum unit nominal frequency ? ? 24.000 ? mhz oscillation mode ? fundamental ? frequency tolerance @25c ? 10 ? ppm tolerance stability over temp @0c to +70c ? 10 ? ppm equivalent series resistance ? ? ? 50 w load capacitance ? ? 12 ? pf operating temperature range ? 0 ? +70 c storage temperature range ? ?40 ? +125 c drive level ? ? ? 200 w aging ? ??10ppm/year shunt capacitance ? ? ? 2 pf c2 c1 r1 32.768 khz xtal
gpio port broadcom september 9, 2013 ? 20730-ds108-r page 27 ? bcm20730 data sheet broadcom confidential gpio port the bcm20730 has 14 general-purpose i/os (gpios) in the 32-pin package, 22 gpios in the 40-pin package, and 40 gpios in the 64-pin package. all gpios support programmable pull-up and pull-down resistors, and all support a 2 ma drive strength except p26, p27, p28, and p29, which provide a 16 ma drive strength at 3.3v supply. port 0?port 1, port 8?port 23, and port 28?port 38 all of these pins can be programmed as adc inputs. port 26?port 29 p[26:29] consists of four pins. all pins are capable of sinking up to 16 ma for led. these pins also have the pwm function, which can be used for led dimming. pwm the bcm20730 has four internal pwm channels. the pwm module consists of the following: ?pwm1?4 ? each of the four pwm channels, pwm1?4, contains the following registers: ? 10-bit initial value register (read/write) ? 10-bit toggle register (read/write) ? 10-bit pwm counter value register (read) table 6: xtal oscillator characteristics parameter symbol conditions minimum typical maximum unit output frequency f oscout ? ? 32.768 ? khz frequency tolerance ? crystal dependent ? 100 ? ppm start-up time t startup ???500ms xtal drive level p drv for crystal selection 0.5 ? ? w xtal series resistance r series for crystal selection ?? 70k xtal shunt capacitance c shunt for crystal selection ?? 1.3pf
power management unit broadcom september 9, 2013 ? 20730-ds108-r page 28 ? bcm20730 data sheet broadcom confidential ? the pwm configuration register is shared among pwm1?4 (read/write). this 12-bit register is used: ? to configure each pwm channel. ? to select the clock of each pwm channel ? to change the phase of each pwm channel figure 8 shows the structure of one pwm channel. figure 8: pwm channel block diagram power management unit the power management unit (pmu) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. rf power management the bbc generates power-down control signals for the tr ansmit path, receive path, pll, and power amplifier to the 2.4 ghz transceiver, which then proc esses the power-down functions accordingly. pwm_cfg_adr register pwm#_init_val_adr register pwm#_togg_val_adr register pwm#_cntr_adr enable cntr value is cm3 readable clk_sel o_flip 10'h000 10'h3ff 10 10 10 example: pwm cntr w/ pwm#_init_val = 0 (dashed line) pwm cntr w/ pwm#_init_val = x (solid line) 10'hx pwm_out pwm_togg_val_adr pwm_out
power management unit broadcom september 9, 2013 ? 20730-ds108-r page 29 ? bcm20730 data sheet broadcom confidential host controller power management power is automatically managed by the firmware based on input device activity. as a power-saving task, the firmware controls the disabling of the on-chip regulator when in deep sleep mode. bbc power management there are several low-power operations for the bbc: ? physical layer packet handling turns rf on and off dynamically within packet tx and rx. ? bluetooth-specified low-power connection sniff mode. while in these low-power connection modes, the bcm20730 runs on the low power oscillator and wakes up after a predefined time period. the bcm20730 automatically adjusts its power dissipation based on user activity. the following power modes are supported: ?active mode ?idle mode ?sleep mode ? hidoff mode the bcm20730 transitions to the next lower state after a programmable period of user inactivity. busy mode is immediately entered when user activity resumes. in hidoff mode, the bcm20730 baseband and core are powered off by disabling power to ldoout. the vddo domain remains powered up and will turn the remainder of the chip on when it detects user events. this mode minimizes chip power consumption and is intended for long periods of inactivity.
pin assignments broadcom september 9, 2013 ? 20730-ds108-r page 30 ? bcm20730 data sheet broadcom confidential section 2: pin assignments pin descriptions table 7: pin descriptions pin number pin name i/o power domain description 32-pin qfn 40-pin qfn 64-pin bga radio i/o 6 8 f1 rf i/o vdd_rf rf antenna port rf power supplies 4 6 d1 vddif i vdd_rf ifpll power supply 5 7 e1 vddfe i vdd_rf rf front-end supply 7 9 h1 vddvco i vdd_rf vco, logen supply 8 10 h2 vddpll i vdd_rf rfpll and crystal oscillator supply power supplies 11 13 h6 vddc i n/a baseband core supply ??d4, e2, e5, f2, g1, g2 vss i n/a ground 28 34 a6, d7 vddo i vddo i/o pad and core supply 14 16 ? vddm i vddm i/o pad supply clock generator and crystal interface 9 11 h3 xtali i vdd_rf crystal oscillator input. see ?crystal oscillator? on page 25 for options. 10 12 g3 xtalo o vdd_rf crystal oscillator output. 1 40 a3 xtali32k i vddo low-power oscillator (lpo) input is used. alternative function: ? p11 and p27 in 32-qfn only ? p11 in 40-qfn only ? p39 in 64-bga only 32 39 b3 xtalo32k o vddo low-power oscillator (lpo) output. alternative function: ? p12 and p26 in 32-qfn only ? p12 in 40-qfn only ? p38 in 64-bga only
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 31 ? bcm20730 data sheet broadcom confidential core 18 20 g8 reset_n i/o pu vddo active-low system reset with open- drain output & internal pull-up resistor 17 19 g7 tmc i vddo test mode control high: test mode connect to gnd if not used. uart 12 14 h5 uart_rxd i vddm a uart serial input ? serial data input for the hci uart interface. leave unconnected if not used. alternative function: ?gpio3 13 15 g5 uart_txd o, pu vddm a uart serial output ? serial data output for the hci uart interface. leave unconnected if not used. alternative function: ?gpio2 bsc 15 17 f7 sda i/o, pu vddm a data signal for an external i 2 c device. alternative function: ? spi_1: mosi (master only) ?gpio0 ?cts 16 18 e8 scl i/o, pu vddm a clock signal for an external i 2 c device. alternative function: ? spi_1: spi_clk (master only) ?gpio1 ?rts ldo regulator power supplies 2 4 b1 ldoin i ldo battery input supply for the ldo 3 5 c1 ldoout o ldo ldo output a. vddo for 64-pin package. table 7: pin descriptions (cont.) pin number pin name i/o power domain description 32-pin qfn 40-pin qfn 64-pin bga
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 32 ? bcm20730 data sheet broadcom confidential table 8: gpio pin descriptions a pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga 19 21 f6 p0 input floating vddo ? gpio: p0 ? keyboard scan input (row): ksi0 ? a/d converter input ? peripheral uart: puart_tx ? spi_2: mosi (master and slave) ? ir_rx ?60 hz_main ? not available during tmc=1 20 22 g6 p1 input floating vddo ? gpio: p1 ? keyboard scan input (row): ksi1 ? a/d converter input ? peripheral uart: puart_rts ? spi_2: miso (master and slave) ?ir_tx 22 24 h8 p2 input floating vddo ? gpio: p2 ? keyboard scan input (row): ksi2 ? quadrature: qdx0 ? peripheral uart: puart_rx ?triac control 2 ? spi_2: spi_cs (slave only) ? spi_2: spi_mosi (master only) 21 23 f8 p3 input floating vddo ? gpio: p3 ? keyboard scan input (row): ksi3 ? quadrature: qdx1 ? peripheral uart: puart_cts ? spi_2: spi_clk (master and slave) 23 25 h7 p4 input floating vddo ? gpio: p4 ? keyboard scan input (row): ksi4 ? quadrature: qdy0 ? peripheral uart: puart_rx ? spi_2: mosi (master and slave) ?ir_tx ? 26 e6 p5 input floating vddo ? gpio: p5 ? keyboard scan input (row): ksi5 ? quadrature: qdy1 ? peripheral uart: puart_tx ? spi_2: miso (master and slave)
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 33 ? bcm20730 data sheet broadcom confidential ?27f5p6 pwm2 input floating vddo ? gpio: p6 ? keyboard scan input (row): ksi6 ? quadrature: qdz0 ? peripheral uart: puart_rts ? spi_2: spi_cs (slave only) ?60hz_main ?triac control 1 ? 28 c5 p7 input floating vddo ? gpio: p7 ? keyboard scan input (row): ksi7 ? quadrature: qdz1 ? peripheral uart: puart_cts ? spi_2: spi_clk (master and slave) 24 29 f4 p8 input floating vddo ? gpio: p8 ? keyboard scan output (column): kso0 ? a/d converter input ? external t/r switch control: ~tx_pd alternative function: ? p33 in 32-qfn only ? 3 a1 p9 input floating vddo ? gpio: p9 ? keyboard scan output (column): kso1 ? a/d converter input ? external t/r switch control: tx_pd ?2d2p10 pwm3 input floating vddo ? gpio: p10 ? keyboard scan output (column): kso2 ? a/d converter input 1 40 c2 p11 input floating vddo ? gpio: p11 ? keyboard scan output (column): kso3 ? a/d converter input ? xtali32k (32-qfn and 40-qfn only) alternative function: ? p27 in 32-qfn only table 8: gpio pin descriptions a (cont.) pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 34 ? bcm20730 data sheet broadcom confidential 32 39 b2 p12 input floating vddo ? gpio: p12 ? keyboard scan output (column): kso4 ? a/d converter input ? xtalo32k (32-qfn and 40-qfn only) alternative function: ? p26 in 32-qfn only 29 35 f3 p13 pwm3 input floating vddo ? gpio: p13 ? keyboard scan output (column): kso5 ? a/d converter input ?triac control 3 alternative function: ? p28 in 32-qfn only 30 36 d3 p14 pwm2 input floating vddo ? gpio: p14 ? keyboard scan output (column): kso6 ? a/d converter input ?triac control 4 alternative function: ? p38 in 32-qfn only 31 37 a2 p15 input floating vddo ? gpio: p15 ? keyboard scan output (column): kso7 ? a/d converter input ? ir_rx ?60hz_main ? ? c8 p16 input floating vddo ? gpio: p16 ? keyboard scan output (column): kso8 ? ? h4 p17 input floating vddo ? gpio: p17 ? keyboard scan output (column): kso9 ? a/d converter input ? ? c7 p18 input floating vddo ? gpio: p18 ? keyboard scan output (column): kso10 ? a/d converter input table 8: gpio pin descriptions a (cont.) pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 35 ? bcm20730 data sheet broadcom confidential ? ? b8 p19 input floating vddo ? gpio: p19 ? keyboard scan output (column): kso11 ? a/d converter input ? ? a8 p20 input floating vddo ? gpio: p20 ? keyboard scan output (column): kso12 ? a/d converter input ? ? c6 p21 input floating vddo ? gpio: p21 ? keyboard scan output (column): kso13 ? a/d converter input ?triac control 3 ? ? g4 p22 input floating vddo ? gpio: p22 ? keyboard scan output (column): kso14 ? a/d converter input ?triac control 4 ? ? e3 p23 input floating vddo ? gpio: p23 ? keyboard scan output (column): kso15 ? a/d converter input 27 33 a7 p24 input floating vddo ? gpio: p24 ? keyboard scan output (column): kso16 ? spi_2: spi_clk (master and slave) ? spi_1: miso (master only) ? peripheral uart: puart_tx 26 32 b7 p25 input floating vddo ? gpio: p25 ? keyboard scan output (column): kso17 ? spi_2: miso (master and slave) ? peripheral uart: puart_rx table 8: gpio pin descriptions a (cont.) pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 36 ? bcm20730 data sheet broadcom confidential 32 38 a4 p26 pwm0 input floating vddo ? gpio: p26 ? keyboard scan output (column): kso18 ? spi_2: spi_cs (slave only) ? spi_1: miso (master only) ? optical control output: qoc0 ?triac control 1 alternative function: ? p12 in 32-qfn only current: 16 ma 11b4p27 pwm1 input floating vddo ? gpio: p27 ? keyboard scan output (column): kso19 ? spi_2: mosi (master and slave) ? optical control output: qoc1 ?triac control 2 alternative function: ? p11 in 32-qfn only current: 16 ma 29 ? b5 p28 pwm2 input floating vddo ? gpio: p28 ? optical control output: qoc2 ? a/d converter input ?led1 ?ir_tx alternative function: ? p13 in 32-qfn only current: 16 ma ??a5p29 pwm3 input floating vddo ? gpio: p29 ? optical control output: qoc3 ? a/d converter input ?led2 ? ir_rx current: 16 ma ? ? e4 p30 input floating vddo ? gpio: p30 ? a/d converter input ? pairing button pin in default fw ? peripheral uart: puart_rts table 8: gpio pin descriptions a (cont.) pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 37 ? bcm20730 data sheet broadcom confidential ? ? e7 p31 input floating vddo ? gpio: p31 ? a/d converter input ? eeprom wp pin in default fw ? peripheral uart: puart_tx 25 31 d6 p32 input floating vddo ? gpio: p32 ? a/d converter input ? quadrature: qdx0 ? spi_2: spi_cs (slave only) ? spi_1: miso (master only) ? auxiliary clock output: aclk0 ? peripheral uart: puart_tx 24 30 d8 p33 input floating vddo ? gpio: p33 ? a/d converter input ? quadrature: qdx1 ? spi_2: mosi (slave only) ? auxiliary clock output: aclk1 ? peripheral uart: puart_rx alternative function: ? p8 in 32-qfn only ? ? b6 p34 input floating vddo ? gpio: p34 ? a/d converter input ? quadrature: qdy0 ? peripheral uart: puart_rx ? external t/r switch control: tx_pd ? ? d5 p35 input floating vddo ? gpio: p35 ? a/d converter input ? quadrature: qdy1 ? peripheral uart: puart_cts ? ? c4 p36 input floating vddo ? gpio: p36 ? a/d converter input ? quadrature: qdz0 ? spi_2: spi_clk (master and slave) ? auxiliary clock output: aclk0 ? battery detect pin in default fw ? external t/r switch control: ~tx_pd table 8: gpio pin descriptions a (cont.) pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
pin descriptions broadcom september 9, 2013 ? 20730-ds108-r page 38 ? bcm20730 data sheet broadcom confidential ? ? c3 p37 input floating vddo ? gpio: p37 ? a/d converter input ? quadrature: qdz1 ? spi_2: miso (slave only) ? auxiliary clock output: aclk1 30 ? b3 p38 input floating vddo ? gpio: p38 ? a/d converter input ? spi_2: mosi (master and slave) ?ir_tx ?xtalo32k (64-bga only) alternative function: ? p14 in 32-qfn only ? ? a3 p39 input floating vddo ? gpio: p39 ? spi_2: spi_cs (slave only) ? spi_1: miso (master only) ? infrared control: ir_rx ? external pa ramp control: pa_ramp ? xtali32k (64-bga only) ?60hz_main a. during power-on reset, all inputs are disabled. table 8: gpio pin descriptions a (cont.) pin number pin name default direction after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
ball maps broadcom september 9, 2013 ? 20730-ds108-r page 39 ? bcm20730 data sheet broadcom confidential ball maps figure 9: 32-pin qfn ball map 1 2 3 4 5 6 7 8 9 10111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p11/p27/xtali32k ldo_in ldo_out vddif vddfe rf vddvco vddpll xtali xtalo vddc uart_rxd uart_txd vddm sda scl tmc rst_n p0 p1 p3 p2 p4 p8/p33 p32 p25 p24 vddo p13/p28 p14/p38 p15 p12/p26/xtalo32k
ball maps broadcom september 9, 2013 ? 20730-ds108-r page 40 ? bcm20730 data sheet broadcom confidential figure 10: 40-pin qfn ball map 1 p27/pwm1 p10 p9 ldoin ldoout vddif vddfe rf vddvco vddpll 2 3 4 5 6 7 8 9 10 xtali xtalo vddc uart_rxd uart_txd vddm sda scl tmc reset_n 11 12 13 14 15 16 17 18 19 20 p33 p8 p7 p6 p5 p4 p2 p3 p1 p0 30 29 28 27 26 25 24 23 22 21 xtali32k/p11 xtalo32k/p12 p26/pwm0 p15 p14 p13 vddo p24 p25 p32 40 39 38 37 36 35 34 33 32 31
ball maps broadcom september 9, 2013 ? 20730-ds108-r page 41 ? bcm20730 data sheet broadcom confidential figure 11: 64-pin bga ball map p9 p15 p39/ xtali32k p26/ pwm0 p29/ pwm3 vddo p24 p20 ldoin p12 p38/ xtalo32k p27/ pwm1 p28/ pwm2 p34 p25 p19 ldoout p11 p37 p36 p7 p21 p18 p16 vddif p10 p14 vss p35 p32 vddo p33 vddfe vss p23 p30 vss p5 p31 scl rf vss p13 p8 p6 p0 sda p3 vss vss xtalo p22 uart_ txd p1 tmc reset _n vddvco vddpll xtali p17 uart_ rxd vddc p4 p2 a b c d e f g h 12345678 12345678 e f g h a b c d
specifications broadcom september 9, 2013 ? 20730-ds108-r page 42 ? bcm20730 data sheet broadcom confidential section 3: specifications electrical characteristics table 9 shows the maximum electrical rating for voltages referenced to vdd pin. table 10 shows the power supply characteristics for the range t j = 0 to 125c. table 9: maximum electrical rating rating symbol value unit dc supply voltage for rf domain ? 1.4 v dc supply voltage for core domain ? 1.4 v dc supply voltage for vddm domain (uart/i 2 c) ? 3.8 v dc supply voltage for vddo domain ? 3.8 v dc supply voltage for vr3v ? 3.8 v dc supply voltage for vddfe ? 1.4 v voltage on input or output pin ? v ss ? 0.3 to v dd + 0.3 v operating ambient temperature range topr 0 to +70 c storage temperature range tstg ?40 to +125 c table 10: power supply parameter minimum a a. overall performance degrades beyond minimum and maximum supply voltages. typical maximum a unit dc supply voltage for rf 1.14 1.2 1.26 v dc supply voltage for core 1.14 1.2 1.26 v dc supply voltage for vddm (uart/i 2 c) 1.62 ? 3.63 v dc supply voltage for vddo 1.62 ? 3.63 v dc supply voltage for ldoin 1.425 ? 3.63 v dc supply voltage for vddfe 1.14 1.2 b b. 1.2v for class 2 output with internal vreg. 1.26 v supply noise for vddo (peak-to-peak) ? ? 100 mv supply noise for ldoin (peak-to-peak) ? ? 100 mv
electrical characteristics broadcom september 9, 2013 ? 20730-ds108-r page 43 ? bcm20730 data sheet broadcom confidential table 12 shows the digital level characteristics for (vss = 0v). table 11: ldo regulator electrical specifications parameter conditions min typ max unit input voltage range ? 1.425 ? 3.63 v default output voltage ? ? 1.2 ? v output voltage range 0.8 ? 1.4 v step size ? 40 or 80 ? mv accuracy at any step ?5 ? +5 % load current ? ??30ma line regulation vin from 1.425 to 3.63v, i load = 30 ma ?0.2 ? 0.2 %v o /v load regulation i load from 1 a to 30 ma, vin = 3.3v, bonding r = 0.3 ?0.10.2%v o /ma quiescent current no load @vin = 3.3v *current limit enabled ?6?a power-down current vin = 3.3v, worst@70c ? 5 200 na
electrical characteristics broadcom september 9, 2013 ? 20730-ds108-r page 44 ? bcm20730 data sheet broadcom confidential table 12: adc specifications parameter symbol conditions min typ max unit adc characteristics number of input channels ?? ?28?? channel switching rate f ch ? ? ? 133.33 kch/s input signal range v inp ?0?3.63v reference settling time ? changing refsel 7.5 ? ? s input resistance r inp effective, single-ended ? 500 ? k input capacitance c inp ???5pf conversion rate f c ?5.859?187khz conversion time t c ? 5.35 ? 170.7 s resolution r ? ? 16 ? bits effective number of bits ?? ?see table 1 on page 18 ? absolute voltage measurement error ? using on-chip adc firmware driver ?2? % current i i avdd1p2 + i avdd3p3 ?? 1 ma power p ? ? 1.5 ? mw leakage current i leakage t = 25c ? ? 100 na power-up time t powerup ? ? ? 200 s integral nonlinearity 3 inl ? ?1 ? 1 lsb a a. lsbs are expressed at the 10-bit level. differential nonlinearity a dnl ? ?1 ? 1 lsb a table 13: digital level a a. this table is also applicable to vddmem domain. characteristics symbol min typ max unit input low voltage v il ??0.4v input high voltage v ih 0.75 vddo ? ? v input low voltage (vddo = 1.62v) v il ??0.4v input high voltage (vddo = 1.62v) v ih 1.2 ? ? v output low voltage b b. at the specified drive current for the pad. v ol ??0.4v output high voltage b v oh vddo ? 0.4 ? ? v input capacitance (vddmem domain) c in ?0.12?pf
electrical characteristics broadcom september 9, 2013 ? 20730-ds108-r page 45 ? bcm20730 data sheet broadcom confidential table 14: current consumption a a. current consumption measurements are taken at vbat with the assumption that vbat is connected to vddio and ldoin. operational mode conditions typ max unit receive receiver and baseband are both operating, 100% on. ?26.6 ma transmit transmitter and baseband are both operating, 100% on. ?24 at 2 dbm, 19 at 0 dbm ma dm1 average current when the device is in the transmit state, 100% utilization of available slots. 15.2 ? ma dh1 average current when the device is in the receive state, 100% utilization of available slots. 16.67 ? ma sleep internal lpo is in use. 28.4 ? a hidoff ? 1.5 ? a sniff mode, 11.25 ms slave 2.8 ? ma sniff mode, 22.5 ms slave 1.27 ? ma sniff mode, 60 ms slave 750 ? a sniff mode, 100 ms slave 500 ? a sniff mode, 495 ms slave 125 ? a caution! this device is susceptible to permanent damage from electrostatic discharge (esd). proper precautions are required during handling and mounting to avoid excessive esd. table 15: esd tolerance model tolerance human body model (hbm) 2000v charged device model (cdm) 400v machine model (mm) 150v
rf specifications broadcom september 9, 2013 ? 20730-ds108-r page 46 ? bcm20730 data sheet broadcom confidential rf specifications table 16: receiver rf specifications parameter mode and conditions min typ max unit receiver section frequency range ? 2402 ? 2480 mhz rx sensitivity (standard) gfsk, 0.1%ber, 1 mbps ? ?88.0 ?84.0 dbm rx sensitivity (low current) ? ?84.0 ? dbm input ip3 ? ?16 ? ? dbm maximum input ? ?10 ? ? dbm interference performance c/i cochannel gfsk, 0.1%ber a a. desired signal is 10 db above the reference sensitivity level (defined as ?70 dbm). ??11.0db c/i 1 mhz adjacent channel gfsk, 0.1%ber a ??0.0db c/i 2 mhz adjacent channel gfsk, 0.1%ber a ? ? ?30.0 db c/i 3 mhz adjacent channel gfsk, 0.1%ber b b. desired signal is 3 db above the reference sensitivity level (defined as ?70 dbm). ? ? ?40.0 db c/i image channel gfsk, 0.1%ber a ???9.0db c/i 1 mhz adjacent to image channel gfsk, 0.1%ber a ? ? ?20.0 db out-of-band blocking performance (cw) b 30 mhz to 2000 mhz 0.1%ber ? ?10.0 ? dbm 2000 mhz to 2399 mhz 0.1%ber ? ?27 ? dbm 2498 mhz to 3000 mhz 0.1%ber ? ?27 ? dbm 3000 mhz to 12.75 ghz 0.1%ber ? ?10.0 ? dbm spurious emissions 30 mhz to 1 ghz ? ? ? ?57.0 dbm 1 ghz to 12.75 ghz ? ? ? ?55.0 dbm
rf specifications broadcom september 9, 2013 ? 20730-ds108-r page 47 ? bcm20730 data sheet broadcom confidential table 17: transmitter rf specifications parameter min typ max unit transmitter section frequency range 2402 ? 2480 mhz output power adjustment range ?6.0 ? 4.0 dbm default output power ? 4.0 ? dbm output power variation ? 2.0 ? db 20 db bandwidth ? 900 1000 khz adjacent channel power |m ? n| = 2 ? ? ?20 dbm |m ? n| 3? ? ?40dbm out-of-band spurious emission 30 mhz to 1 ghz ? ? ?36.0 dbm 1 ghz to 12.75 ghz ? ? ?30.0 dbm 1.8 ghz to 1.9 ghz ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ?47.0 dbm lo performance initial carrier frequency tolerance ? ? 75 khz frequency drift dh1 packet ? ? 25 khz dh3 packet ? ? 40 khz dh5 packet ? ? 40 khz drift rate ? ? 20 khz/50 s frequency deviation average deviation in payload (sequence used is 00001111) 140 ? 175 khz maximum deviation in payload (sequence used is 10101010) 115 ? ? khz channel spacing ? 1 ? mhz
timing and ac characteristics broadcom september 9, 2013 ? 20730-ds108-r page 48 ? bcm20730 data sheet broadcom confidential timing and ac characteristics in this section, use the numbers listed in the reference column of each table to interpret the following timing diagrams. uart timing figure 12: uart timing table 18: uart timing specifications reference characteristics min max unit 1 delay time, uart_cts_n low to uart_txd valid ? 24 baud out cycles 2 setup time, uart_cts_n high before midpoint of stop bit ? 10 ns 3 delay time, midpoint of stop bit to uart_rts_n high ? 2 baud out cycles
timing and ac characteristics broadcom september 9, 2013 ? 20730-ds108-r page 49 ? bcm20730 data sheet broadcom confidential spi timing the spi interface supports clock speeds up to 12 mhz with vddio 2.2v. the supported clock speed is 6 mhz when 2.2v vddio 1.62v. figure 13 shows the timing diagram. spi timing values for different values of sclk and vddm are shown in table 19 , table 20 on page 50 , table 21 on page 50 , table 22 on page 51 . figure 13: spi timing diagram table 19: spi1 timing values ? sclk = 12 mhz and vddm = 3.2v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 12 mhz. the speed can be adjusted to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf/1 m ? load and sclk = 12 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 20 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 63 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns mosi 1 2 3 4 sclk mode 1 miso cs 5 invalid bit msb msb lsb lsb 6 sclk mode 3
timing and ac characteristics broadcom september 9, 2013 ? 20730-ds108-r page 50 ? bcm20730 data sheet broadcom confidential table 20: spi1 timing values ? sclk = 6 mhz and vddm = 1.62v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 6 mhz. the speed can be adjusted to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf/1 m ? load and sclk = 6 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 41 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 120 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns table 21: spi2 timing values ? sclk = 12 mhz and vddm = 3.2v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 12 mhz. the speed can be adjusted to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf//1 m ? load and sclk = 12 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 26 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 56 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled in master mode and can be adjusted as required in slave mode. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns
timing and ac characteristics broadcom september 9, 2013 ? 20730-ds108-r page 51 ? bcm20730 data sheet broadcom confidential bsc interface timing table 22: spi2 timing values ? sclk = 6 mhz and vddm = 1.62v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 6 mhz. the speed can be adjusted to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf//1 m ? load and sclk = 6 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 50 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 120 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled in master mode and can be adjusted as required in slave mode. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns table 23: bsc interface timing specifications reference characteristics min max unit 1 clock frequency ? 100 khz 400 800 1000 2 start condition setup time 650 ? ns 3 start condition hold time 280 ? ns 4 clock low time 650 ? ns 5 clock high time 280 ? ns 6 data input hold time a a. as a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of scl to avoid unintended generation of start or stop conditions. 0 ? ns 7 data input setup time 100 ? ns 8 stop condition setup time 280 ? ns 9 output valid from clock ? 400 ns 10 bus free time b b. time that the cbus must be free before a new transaction can start. 650 ? ns
timing and ac characteristics broadcom september 9, 2013 ? 20730-ds108-r page 52 ? bcm20730 data sheet broadcom confidential figure 14: bsc interface timing diagram
mechanical information broadcom september 9, 2013 ? 20730-ds108-r page 53 ? bcm20730 data sheet broadcom confidential section 4: mechanical information figure 15: 32-pin qfn package
mechanical information broadcom september 9, 2013 ? 20730-ds108-r page 54 ? bcm20730 data sheet broadcom confidential figure 16: 40-pin qfn package
mechanical information broadcom september 9, 2013 ? 20730-ds108-r page 55 ? bcm20730 data sheet broadcom confidential figure 17: 64-pin fbga package
mechanical information broadcom september 9, 2013 ? 20730-ds108-r page 56 ? bcm20730 data sheet broadcom confidential tape reel and packaging specifications the top left corner of the bcm20730 package is situated near the sprocket holes, as shown in figure 18 . table 24: bcm20730 5 5 1 mm qfn, 32-pin tape reel specifications parameter value quantity per reel 2500 pieces reel diameter 13 inches hub diameter 7 inches tape width 12 mm tape pitch 8 mm table 25: bcm20730 6 6 1 mm qfn, 40-pin tape reel specifications parameter value quantity per reel 4000 pieces reel diameter 13 inches hub diameter 4 inches tape width 16 mm tape pitch 12 mm table 26: bcm20730 7 7 0.8 mm wfbga, 64-pin tape reel specifications parameter value quantity per reel 2500 pieces reel diameter 13 inches hub diameter 4 inches tape width 16 mm tape pitch 12 mm
mechanical information broadcom september 9, 2013 ? 20730-ds108-r page 57 ? bcm20730 data sheet broadcom confidential figure 18: pin 1 orientation pin 1: top left corner of package toward sprocket holes
ordering information broadcom september 9, 2013 ? 20730-ds108-r page 58 ? bcm20730 data sheet broadcom confidential section 5: ordering information table 27: ordering information part number package ambient operating temperature bcm20730a2kml2g 32-pin qfn 0c to 70c bcm20730a2kmlg 40-pin qfn 0c to 70c bcm20730a2kfbg 64-pin bga 0c to 70c bcm20730a1kml2g 32-pin qfn 0c to 70c bcm20730a1kmlg 40-pin qfn 0c to 70c bcm20730a1kfbg 64-pin bga 0c to 70c
acronyms and abbreviations broadcom september 9, 2013 ? 20730-ds108-r page 59 ? bcm20730 data sheet broadcom confidential appendix a: acronyms and abbreviations the following list of acronyms and abbreviations may appear in this document. term description adc analog-to-digital converter afh adaptive frequency hopping ahb advanced high-performance bus apb advanced peripheral bus apu audio processing unit arm7tdmi-s? acorn risc machine 7 thumb instruction, debugger, multiplier, ice, synthesizable bsc broadcom serial control btc bluetooth controller coex coexistence dfu device firmware update dma direct memory access ebi external bus interface hci host control interface hv high voltage idc initial digital calibration if intermediate frequency irq interrupt request jtag joint test action group lcu link control unit ldo low drop-out lhl lean high land lpo low power oscillator lv logicvision? mia multiple interface agent pcm pulse code modulation pll phase locked loop pmu power management unit por power-on reset pwm pulse width modulation qd quadrature decoder ram random access memory rf radio frequency
acronyms and abbreviations broadcom september 9, 2013 ? 20730-ds108-r page 60 ? bcm20730 data sheet broadcom confidential rom read-only memory rx/tx receive, transmit spi serial peripheral interface sw software uart universal asynchronous receiver/transmitter upi -processor interface wd watchdog term description
? phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue irvine, ca 92617 ? 2013 by broadcom corporation. all rights reserved. 20730-ds108-r september 9, 2013 broadcom? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm20730 data sheet

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